Emerging nanotechnology for integration of nanostructures in nanoelectronic devices

Scaling down of semiconductor devices is the driving force for the development of new applications (mobile phones, memory cards, sensors, etc.). Up to now, the top-down approach, combining lithography and etching technologies, allowed one to decrease the size of devices. However, we will soon reach the limits of the top-down approach to form nanostructures with uniform properties. In this context, the bottom-up approach, i.e. self-assembly of nanostructures and their direct integration in devices, seems to be a promising way to push towards miniaturization of microelectronic components and towards the creation of new functionalities. In this contribution, we will focus our attention on two emerging nanotechnologies we have developed to fabricate, organize and integrate nanomaterials (nanodots and nanowires) in nanoelectronic devices. The first approach uses the natural properties of diblock copolymers to create (i) a hexagonal lattice array of vertical PMMA cylinders in a PS matrix or (ii) an ordered array of horizontal PMMA cylinders in a PS matrix [1]. These films are then used as deposition and/or etching masks to produce dense lattices of 20 nm diameter nanoparticles and nanowires with a density of ~10 cm. Examples of integration in memory technology fabricated on 200 mm wafers will be shown. The second approach is based on silicon nanowires (NWs) that are often considered as the basic building blocks in future microelectronics (interconnects, transistor channel, nanoelectrodes, etc.), as well as the emerging application areas of photonics, sensors, and energy. We present a study on the CVD catalyzed growth of Si NWs using a fully compatible CMOS process with a silicide [2] as a catalyst and silane as precursor gas. Experimental parameters such as growth temperature, SiH4 partial pressure, and substrate orientation were investigated [3]. Then, Si NWs are positioned or grown directly between electrical contacts. The electrical I(V) measurements show a resistivity around ΜΩ for undoped Si NWs. Mechanical properties will also be shown [4]. Acknowledgments: B. Salem (LTM), M. Kogelschatz (LTM), P. Gentile (SiNAPS), N. Pauc (SiNAPS).